For a fixed channel list, this interleaved ordering can be pre-defined. In most instances, we will want to acquire more than (1) channel of data, so the natural next step for this is to interleave the data that is being written to the FIFO.
LABVIEW FPGA SERIES
As the host is acquiring data from the FPGA, it is guaranteed to be a sequential, ordered series of samples for that channel. In this scenario, you can write the data into the FIFO as it’s being acquired. The simplest scheme for transferring channel data is when you’re acquiring data for a single channel. Using this building block, let’s discuss the progression of a generalized DAQ architecture starting with a single chassis implementation. The DMA FIFO is the fundamental block for lossless transfer of data between an FPGA application and the host. Channel data acquisition times must be synchronized across multiple chasses.Channels may be acquired from different loops that execute at different loop rates.There are a variety of different data types in the channels being acquired.Let's start by outlining our requirements and then build then up a solution which considers several different options for transferring data from the FPGA to the host. We will outline several of these options and present a generalized data transfer mechanism for synchronized DAQ on multiple chassis. There are a lot of ways to use FIFOs for transporting data from the FPGA to the RT target. We use LabVIEW DMA FIFOs for typical FPGA applications that acquire data to be sent to an RT target(Host). In this section, we'll discuss data acquisition using the multiple FPGA chassis architecture outlined in the previous section, NI LabVIEW Part 1: Building Distributed and Synchronized FPGA Applications with Multiple C Series Chassis. If you haven’t already, refer to Part 1 of 3 for Distributed FPGA Chassis Time synchronization.